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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 1MSPS Wide Input Bandwidth: 10MHz Excellent DC Accuracy Performance Flexible Serial Interface Low Power: 90mW (Full-Power) and 5mW (NAP Mode) Standby Mode: 1A max Internal +2.5V Reference Full-Scale Overrange Indication
VREF3 BUF
1MSPS Serial, 14-Bit SAR ADC AD7485
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND CBIAS DVDD DGND VREF1 VREF2 2.5 V REFERENCE
VIN
T/H
14-Bit Error Correcting SAR
AD7485
NAP STBY
MCLK TFS SCO SDO SMODE
GENERAL DESCRIPTION
RESET CONVST VDRIVE
CONTROL LOGIC AND I/O REGISTERS
The AD7485 is a 14-bit, high speed, low power, successive-approximation ADC. The part features a serial interface with throughput rates up to 1MSPS. The part contains a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 10MHz. The conversion process is a proprietary algorithmic successive-approximation technique. The input signal is sampled and conversion is initiated on the falling edge of a CONVST signal. The conversion process is controlled by an external master clock. Interfacing is via standard serial signal lines making the part directly compatible with microcontrollers and DSPs. The AD7485 provides excellent ac and dc performance specifications. Factory trimming ensures high dc accuracy resulting in very low INL, offset and gain errors. The part uses advanced design techniques to achieve very low power dissipation at high throughput rates. Power consumption in normal mode of operation is 70mW. There are two power-saving modes: a NAP mode, which keeps reference circuitry alive for quick power up, consumes 5mW while a STANDBY mode reduces power consumption to a mere 5W.
The AD7485 features an on-board +2.5V reference but the part can also accomodate an externally-provided +2.5V reference source. The nominal analog input range is 0 to +2.5V The AD7485 also provides the user with overrange indication via a 15th bit. If the analog input range strays outside the 0 to +2.5V input range the 15th data bit is set to a logic high. The AD7485 is powered from a +4.75V to +5.25V supply. The part also provides a VDRIVE pin which allows the user to set the voltage levels for the digital interface lines. The range for this VDRIVE pin is from +2.85V to +5.25V. The part is housed in a 48-pin LQFP package and is specified over a -40C to +85C temperature range.
REV. PrA 01/21/02 9 AM
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD7485-SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)2 Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error2 Gain Error 2 ANALOG INPUT Input Voltage DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage VREF Input DC Leakage Current VREF Input Capacitance VREF Output Voltage VREF Error @ 25C VREF Error TMIN to TMAX VREF Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2,3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) NAP Mode Standby Mode Specification 78 78 -90 TBD TBD TBD 10 10 10MHz typ TBD 14 TBD 1 TBD 1 1.5 1.5 0 +2.5 TBD 10 +2.5 1 TBD +2.5 TBD TBD TBD VDRIVE -1 0.4 TBD TBD
(TA = 25 C, VDD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1MSPS)
Units dB dB dB dB min min max max Test Conditions/Comments FIN = 100kHz Sine Wave
dB typ dB typ ns typ ps typ @ 3 dB @0.1 dB Bits LSB LSB LSB LSB LSB LSB
max typ max typ max max
Guaranteed No Missed Codes to 14 bits
V min Volts max A max pF typ Volts A max pF max V nom mV max mV max k typ V min V max A max pF max 1% for specified performance
0.7 x VDRIVE V min 0.3 x VDRIVE V max TBD A max TBD pF max Straight (Natural) Binary TBD TBD TBD 1 +5 +2.85 +5.25 TBD 14 1 1 -2- ns max ns max Sine Wave Input ns max Full-Scale Step Input MSPS max Volts V min V max mA max mA max mA max A max 5%
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PRELIMINARY TECHNICAL DATA
AD7485
Parameter POWER REQUIREMENTS (continued) Power Dissipation Normal Mode (Operational) NAP Mode Standby Mode
NOTES 1 Temperature ranges as follows: -40C to +85C. 2 See Terminology 3 Sample tested @ +25C to ensure compliance Specifications subject to change without notice.
Specification
Units
Test Conditions/Comments
70 5 5
mW max mW max W max
TIMING CHARACTERISTICS 1,2 All specifications T
Parameter Master Clock Frequency MCLK Period Conversion Time CONVST Low Period CONVST High Period MCLK High Period MCLK Low Period CONVST falling edge to MCLK rising edge CONVST falling edge to MSB valid Data valid before SCO falling edge Data valid after SCO falling edge CONVST rising edge to SDO 3-State CONVST Low Period CONVST High Period TFS falling edge to MCLK rising edge TFS falling edge to SCO rising edge TFS falling edge to MSB valid TFS rising edge to SDO 3-State TFS Low Period TFS High Period MCLK Fall Time MCLK Rise Time MCLK - SCO Delay Symbol f MCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22
(VDD = 5 V 5%, AGND = DGND = 0 V, VREF = Internal; MIN to TMAX and valid for VDRIVE = 2.85 V to 5.25 V unless otherwise noted)
Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Typ Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TBD
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PRELIMINARY TECHNICAL DATA
AD7485
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
PIN CONFIGURATION
AVDD 13
AGND 14
AGND 15
STBY 16
NAP 17
MCLK 18
DGND 19
DGND 20
SDO 21
DGND 22
DGND 23
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7485BST
Temperature Range -40C to +85C
Package Description Low-profile Quad Flat Pack
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7485 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
01/21/02 9 AM REV. PrA
DGND 24
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T B D VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T B D Analog Input Voltage to GND . . . . . . . . . . . . . . . . . T B D Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . T B D Digital Output Voltage to GND . . . . . . . . . . . . . . . . . . T B D REF IN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T B D Input Current to Any Pin Except Supplies . . . . . . . . . T B D Operating Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150C 48-Pin LQFP Package, Power Dissipation . . . . . . . . T B D JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 50C/W 10C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBD
41 CONVST
42 RESET
48 AGND
47 AGND
44 DGND
43 DGND
40 SCO 39 DGND
PIN 1 IDENTIFIER AVDD CBIAS AGND AGND AVDD AGND VIN VREF2 VREF1 1 2 3 4 5 6 7 8 9 36 SMODE 35 TFS 34 DGND 33 DGND 32 VDRIVE 31 DGND 30 DGND 29 DVDD 28 DGND 27 DGND 26 DGND 25 DGND
AD7485
TOP VIEW (Not to Scale)
VREF3 10 AGND 11 AGND 12
38 DGND 37 DGND
46 AVDD
45 DVDD
Option ST-48
PRELIMINARY TECHNICAL DATA
AD7485
PIN FUNCTION DESCRIPTION
Pin Mnemonic AVDD C BIAS AGND VIN VREF1 VREF2 VREF3 STBY NAP DVDD DGND V DRIVE CONVST RESET MCLK SDO
Description Positive power supply for analog circuitry. Decoupling pin for internal bias voltage. A 100nF capacitor should be placed between this pin and AGND. Power supply ground for analog circuitry. Analog input. Single-ended analog input channel. Reference Output. VREF1 connects to the output of the internal 2.5V reference. A 1F capacitor must be placed between this pin and AGND. Reference Input. A 1F capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin. Reference decoupling pin. When using the internal reference, a 100nF must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND. Standby logic input. When this pin is logic high, the device will be placed in Standby mode. See Power Saving Section for further details. Nap logic input. When this pin is logic high, the device will be placed in a very low power mode. See Power Saving Section for further details. Positive power supply for digital circuitry. Ground reference for digital circuitry. Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the interface logic of the AD7485 will operate. Convert Start Logic Input. A conversion is initiated on the falling edge of CONVST signal. The input track/hold amplifier goes from track mode to hold mode and the conversion process commences. Reset Logic Input. A logic 0 on this pin resets the internal state machine and terminates a conversion that may be in progress. Holding this pin low keeps the part in a reset state. Master Clock Input. This is the input for the master clock which controls the conversion cycle. The frequency of this clock may be up to 25MHz. 24 clock cycles are required for each conversion. Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It should be latched into the receiving serial port of the DSP on the falling edge of SCO. The Over-range bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero. Transmit Frame Sync input. In Serial Mode 2, this pin acts as a framing signal for the serial data being clocked out on SDO. A falling edge on TFS brings SDO out of three-state and the data starts to get clocked out on the next rising edge of SCO. Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial Mode 2. See Serial Interface Section for further details. Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from the device. See Serial Interface Section for further details.
TFS
SMODE SCO
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PRELIMINARY TECHNICAL DATA
AD7485
TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7485 it is defined as:
THD (dB ) = 20 log V2 +V3 +V 4 +V5 +V 6 V1
2 2 2 2 2
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e AGND + 0.5 LSB Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF - 1.5 LSB) after the offset error has been adjusted out.
Track/Hold Acquisition Time
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode).
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 14-bit converter, this is 86.04 dB.
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7484 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
-6-
01/21/02 9 AM REV. PrA
PRELIMINARY TECHNICAL DATA
AD7485
CIRCUIT DESCRIPTION CONVERTER OPERATION
The AD7485 is a 14-bit error correcting successive approximation analog-to-digital converter based around a capacitive DAC. It provides the user with track/hold, reference, A/D converter and versatile interface logic functions on a single chip. The analog input signal range that the AD7485 can convert is 0 to 2.5 Volts. The part requires a +2.5V reference which can be provided from the part's own internal reference or an external reference source. Figure 1 shows a very simplified schematic of the ADC. The Control Logic, SAR and the Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition.
At the end of conversion, the track/hold returns to tracking mode and the acquisition time begins. The track/hold acquisition time is TBD nS. Figure 3 shows the ADC during its acquistition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN.
CAPACITIVE DAC
VIN
A
+
SW1
B SW2
CONTROL LOGIC
-
COMPARATOR
COMPARATOR
CAPACITIVE DAC
AGND
Figure 3. ADC Acquisition Phase
ADC TRANSFER FUNCTION
VIN VREF
SWITCHES
SAR
The output coding of the AD7485 is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The LSB size is VREF / 16384. The nominal transfer characteristic for the AD7485 in shown in figure 4 below.
OUTPUT DATA 14-BIT SERIAL
111...11 1 111...11 0
ADC CODE
CONTROL INPUTS
CONTROL LOGIC
Figure 1. Simplified Block Diagram of AD7485
Conversion is initiated on the AD7485 by pulsing the CONVST input. On the falling edge of CONVST, the track/hold goes from track to hold mode and the conversion sequence is started. Conversion time for the part is 24 MCLK periods. Figure 2 shows the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The ADC then runs through its successive approximation routine and brings the comparator back into a balanced condition. When the comparator is rebalanced, the conversion result is available in the SAR register.
111...00 0 011...11 1
1LSB = VREF/16384
000...01 0 000...00 1 000...00 0
0V
0.5LSB
+VREF-1.5LSB
ANALOG INPUT
Figure 4. AD7485 Transfer Characteristic
CAPACITIVE DAC
VIN
A
+
SW1
B SW2
CONTROL LOGIC
-
COMPARATOR
AGND
Figure 2. ADC Conversion Phase
REV. PrA 01/21/02 9 AM
-7-
PRELIMINARY TECHNICAL DATA
AD7485
POWER SAVING
The AD7485 uses advanced design techniques to achieve very low power dissipation at high throughput rates. In addition to this the AD7485 features two power saving modes, Nap Mode and Standby Mode. These modes are selected by bringing either the NAP or STBY pin to a logic high respectively. When operating the AD7485 with a 25MHz MCLK in normal, fully powered mode, the current consumption is 14mA during conversion and the quiescent current is 10mA. Operating at a throughput rate of 500kSPS, the conversion time of 960nS contributes 33.6mW to the overall power dissipation.
(960nS / 2S) x (5V x 14mA) = 33.6mW
1.06S
8.94S
100nS
10S
Figure 6. NAP Mode Power Dissipation
For the remaining 1.04S of the cycle, the AD7485 dissipates 17.5mW of power.
(1.04S / 2S) x (5V x 10mA) = 26mW
Figures 7 and 8 show a typical graphical representation of Power vs. Throughput for the AD7485 when in Normal and Nap modes respectively.
70
Thus the power dissipated during each cycle is:
POWER - mW
65
33.6mW + 26mW = 59.6mW
Figure 5 below shows the AD7485 conversion sequence operating in normal mode.
2 S
60
55
50 0 200 400 600 800 1000
Read Data 960 nS
Conversion Finished 1.04 S
THROUGHPUT - KSPS
Figure 5. Normal Mode Power Dissipation
Figure 7. Normal Mode - Power vs. Throughput
PO WER - m W
In NAP mode, all the internal circuitry except for the internal reference is powered down. In this mode, the power dissipation of the AD7485 is reduced to 5mW. When exiting NAP mode a minimum of 100nS must be waited before initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track/hold to properly acquire the analog input signal. If the AD7485 is put into NAP mode after each conversion, the average power dissipation will be reduced but the throughput rate will be limited by the power-up time. Using the AD7485 with a throughput rate of 100kSPS while placing the part in NAP mode after each conversion would result in average power dissipation as follows: The power-up and conversion phase will contribute 7.42mW to the overall power dissipation.
(1.06S / 10S) x (5V x 14mA) = 7.42mW
60
50
40
30
20
10
0 0 100 200 300 400 500 600 700 THROUGHPUT - KSPS
Figure 8. Nap Mode - Power vs. Throughput
While in NAP mode for the rest of the cycle, the AD7485 dissipates only 4.47mW of power.
(8.94S / 10S) x (5V x 1mA) = 4.47mW
Thus the power dissipated during each cycle is:
7.42mW + 4.47mW = 11.89mW
Figure 6 shows the AD7485 conversion sequence if putting the part into NAP mode after each conversion.
In STANDBY mode, all the internal circuitry is powered down and the power consumption of the AD7485 is reduced to 5W. Because the internal reference has been powered down, the power-up time necessary before a conversion can be initiated is longer. If using the internal reference of the AD7485, the ADC must be brought out of STANDBY mode 200S before a conversion is initiated. Initiating a conversion before the required power-up time has elapsed will result in incorrect conversion data. If an external reference source is used and kept powered up while the AD7485 is in STANDBY mode, the powerup time required will be reduced. -8- 01/21/02 9 AM REV. PrA
PRELIMINARY TECHNICAL DATA
AD7485
SERIAL INTERFACE
The AD7485 has two serial interface modes, selected by the state of the SMODE pin. In both these modes the MCLK pin must be supplied with a clock signal of between TBD MHz and 25MHz. This MCLK signal controls the internal conversion process and is also used to derive the SCO signal. As the AD7485 uses an algorithmic successive-approximation technique, 24 MCLK cycles are required to complete a conversion. Due to the error-correcting operation of this ADC, all bit trials must be completed before the conversion result is calculated. This results in a single sample delay in the result that is clocked out. In serial mode 1 (see Figure 10 for details), the CONVST pin is used to initiate the conversion and also frame the serial data. When CONVST is brought low, the SDO line is taken out of three-state, the over-range bit will be clocked out on the next rising edge of SCO followed by the 14 data bits (MSB first) and a trailing zero. CONVST must remain low for 16 SCO pulses to allow all the data to be clocked out. When CONVST returns to a logic high, the SDO line returns to three-state. TFS should be tied to ground in this mode. In serial mode 2 (see Figure 11 for details), the CONVST pin is used to initiate the conversion but the TFS signal is used to frame the serial data. The duty cycle of the CONVST signal may vary as shown in the timing diagram. This allows the CONVST line to be driven by high precision, 50% duty cycle signal for extremely accurate sampling intervals. TFS must remain low for 16 SCO cycles in this mode to allow all the data to be clocked out. Figure 9 shows a typical connection diagram for the AD7485. In this case the MCLK signal is provided by a 25MHz crystal oscillator module. It could also be provided by the second serial port of a DSP (e.g. ADSP-2189M) if such were available. In Figure 9 the VDRIVE pin is tied to DVDD, which results in logic output levels being either 0 V or DVDD. The voltage applied to VDRIVE controls the voltage value of the output logic signals. For example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic output levels would be either 0 V or 3 V. This feature allows the AD7485 to interface to 3 V devices while still enabling the A/D to process signals at 5 V supply.
1nF
10F
0.1F
47F
ANALOG SUPPLY 4.75V - 5.25V
DVDD VDRIVE AVDD RESET SMODE CBIAS VREF3 VREF2 VREF1 0.1F 0.1F 0.47F 0.47F
C/ P
CONVST TFS SCO SDO NAP STBY
VIN
0V to +2.5V
25MHz XO
AD7485
MCLK
Figure 9. AD7485 Typical Connection Diagram
REV. PrA 01/21/02 9 AM
-9-
PRELIMINARY TECHNICAL DATA
AD7485
t2 t3 t4
t7
t1
t5
t6
t8
t9
t10
t11
Figure 10. Serial Mode 1 (SMODE=0) Read Cycle
t12
t13
t7
t1
t5
t14
t6
t15
t9
t10
t16
t17
t18
t19
t2
Figure 11. Serial Mode 2 (SMODE=10) Read Cycle
t1
t6 t21 t5
t20
t22
Figure 12. Serial Clock Timing
-10-
01/21/02 9 AM REV. PrA
PRELIMINARY TECHNICAL DATA
AD7485
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Pin LQFP Package (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
1
0.354 (9.00) BSC SQ
48 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
08 MIN
12 13 24
0.019 (0.5) BSC 78 08
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
REV. PrA 01/21/02 9 AM
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